1. Field of the Invention
The present invention relates to a signal synchronizing device, more particularly to a signal synchronizing device applicable to a system on a chip (SOC).
2. Description of the Related Art
Since each of multiple logic circuits in a system on a chip is usually required to operate at frequency domains of at least two different clock signals, when signals are transmitted between two logic circuits operating at frequency domains of two different clock signals, the signals must be synchronously processed prior to signal transmission. Otherwise, an issue of meta-stability may occur between the two logic circuits.
Referring to FIG. 1, a conventional signal synchronizing device disclosed in U.S. Pat. No. 7,134,035 B2 is adapted to a system on a chip for transferring an input signal IN which corresponds with frequency domain of a first clock signal CKA into an output signal OUT which is synchronous with respect to frequency domain of a second clock signal CKB. The conventional signal synchronizing device includes a first storage unit F1 and a double synchronizer 1.
The first storage unit F1 receives the first clock signal CKA and the input signal IN, and outputs a first pulse signal which is phase-delayed with respect to the input signal IN by sampling the input signal IN according to the first clock signal CKA.
The double synchronizer 1 is electrically coupled to the first storage unit F1, and includes a second storage unit F2 and a third storage unit F3.
The second storage unit F2 receives the second clock signal CKB and the first pulse signal, and outputs a second pulse signal which is phase-delayed with respect to the input signal IN by sampling the first pulse signal according to the second clock signal CKB.
The third storage unit F3 receives the second clock signal CKB and the second pulse signal, and outputs an output signal OUT which is phase-delayed with respect to the second pulse signal by sampling the second pulse signal according to the second clock signal CKB.
Referring to FIG. 2, a timing diagram of the conventional synchronizing device is illustrated, wherein F10 represents the first pulse signal and F20 represents the second pulse signal.
Since details of the conventional synchronizing device are described in U.S. Pat. No. 7,134,035 B2, they are omitted herein for the sake of brevity.
However, the conventional signal synchronizing device has the following disadvantages:
1. The conventional signal synchronizing device is only applicable to a condition that the frequency of the first clock signal CKA is slower than the frequency of the second clock signal CKB, and thus has a narrower range of applicability. Moreover, since it is required to know in advance which one of the frequencies of the first and second clock signals CKA, CKB in the applied system on a chip is faster, there is inconvenience in use.
2. When the frequency of the first clock signal CKA is faster than that of the second clock signal CKB, and the conventional signal synchronizing device is desired to be adopted, an additional circuit is required for converting the frequency of the first clock signal CKA into another frequency slower than that of the second clock signal CKB. Moreover, another additional circuit (such as a counter) is required to calculate a ratio between frequencies of the first and second clock signals CKA, CKB, so as to know how slow the frequency of the first clock signal CKA is to be converted. Therefore, an increment in hardware costs is incurred.